The ARM1136J-S is synthesised from RTL and comes with timing models and over 99 percent fault coverage is claimed. The firm also offers a reference design with all the peripherals typically needed in an embedded processor application.
The eight-stage pipeline 32-bit Risc core includes a 16kbyte instruction cache, 16kbyte data cache, 16kbyte instruction TCM (tightly-coupled memory) and 16kbyte data TCM. Also included is a memory management unit (MMU) for operating systems such as Linux and 64-bit instruction and data bus interfaces.
The reference design has an interrupt controller, UART, GPIO, timers, internal SRAM, EBIU and APB bridge.