ADC offers multi-microphone beam-forming to ease host processor load

“Smart home systems face challenges with far-field audio capture,” according to TI. “In today’s systems, a limited number of microphones and restricted signal processing capability make it difficult to capture and understand voice commands in loud environments. To meet this challenge, the TLV320ADC5140 enables engineers to improve audio capture from across rooms and boost recognition of soft-spoken commands in applications such as smart speakers, sound bars, wireless speakers, high definition TVs, IP network cameras, teleconferencing systems and smart appliances.”

The chip consists of four analogue audio channels, each with a 120dB dynamic range programmable gain front-end amplifier (differential or single-ended inputs), followed by multi-channel multi-bit 108dB dynamic range ΔΣ ADC. A bias power supply is available to feed up to 20mA to mics that need a power source.

Following this is a host of digital signal processing – more of this later.

Why a 120dB amplifier and a 108dB ADC?

The answer is that it has a “built-in 120dB dynamic range enhancer [‘DRE’]. At a system level, the DRE scheme boosts low-volume audio signals while maintaining low-distortion recordings, even at close proximity to the speaker output,” said TI.

You have to dig to page 50 of the data sheet to find out what DRE actually is, and it is “a digitally assisted algorithm. The DRE monitors the incoming signal amplitude and accordingly adjusts the programmable gain amplifier gain automatically. This algorithm is implemented with low latency and signal chain blocks are designed to minimise any audible artifacts that may occur resulting from dynamic gain modulation”.

The ADC has inherent anti-alias filtering that can reject out-of-band noise, preventing it from being flipped in-band by sampling, followed by a multi-stage digital decimation filter with high stop-band attenuation.

There is also a programmable digital bi-quad filter that allows for custom low-pass or high-pass behaviour, or other desired frequency shaping.

Also in the digital signal chain is: phase calibration (163ns resolution), gain calibration, digital summing (or mixing) and a volume control.

Control from the host processor is through I2C or SPI interfaces, and the device supports a flexible audio serial interface for TDM (time-division multiplexing), I2S, or left-justified (LJ). Multiple devices can share common I2C and TDM buses, and there is a secondary audio serial output data pin.

Inputs up to 80kHz are supported, allowing high-frequency non-audio signal to be recorded by using a 176.4kHz (or higher – it goes to 768kHz) sample rates.

For output sample rates of 48kHz or below, the device supports all features for eight-channel recording.

For output sample rates higher than 48kHz, there are limitations in the number of simultaneous channels supported and the number of bi-quad filters.

Power consumption varies depending on how the internal blocks are programmend, but can be as low as 9.5mW per channel at 48kHz.

It is available now, in a 4 x 4mm 24pin WQFN, as is a quad-channel 768kHz evaluation module and a PDK.